Schedule for the design and tests of the DAQ

The immediate goal should be, to develop the architecture of the DAQ system within the year 1996 to a level, where a first test setup can be fixed. This test setup should then be assembled within 1997. Apart from allowing to gather experience with its components this system should also serve as testbeam DAQ if possible. The availability of the components is as follows:

• The DAQ machine will be bought only as late as possible to have processors of an as high performance as possible. However a single processor workstation with PCI slots should be available at CERN by next year. It should be preferably of the same brand as the projected DAQ machine to have compatibility of interfaces and software.
  A 6 processor AlphaServer 8200 with the same I/O capabilities as the projected DAQ machine is currently operated at the MPI Heidelberg and could be made available for short I/O tests at.
• There are several options for the interfaces used to transfer data from the large spill buffers to the DAQ machine. The company Genroco already provides FibreChannel interfaces for PCI slots on Digital workstations and for PMC slots on VME modules running at rates of 100MB/s. HiPPI interfaces for Digital workstations are available as well, their PMC counterparts are under development.
  Interfaces for SCI-PCI and SCI-PMC are about to be manufactured commercially and will be available by beginning of the year 1997.
• The proposed main memory and I/O module MIDAS 100 by VMETRO will be available by the end of the third quarter 1996. Technical briefings on this module have already taken place at CERN.

The further development of the detector readout electronics should follow this architecture and will be included into the setup, when ready. This should be completed for all detectors by mid 1998 to a level, that first tests of all the various types of detector readout systems can be performed.

  
Figure 3.8: The data flow of the proposed data acquisition system. The first level consists of the frontend electronics mostly mounted close to the various detectors. The second level consists of large memory modules in VME controlled by simple processors. Master CPUs provide run control, slow control software links etc. The third level is the DAQ machine, which does event building and online filtering.